06/02/2012 01:42 PM
Generates a fixed frequency clock and reset signal. You can use the clock via top level testbench just like any other modules. Using reset (active low) is optional. I am using that in my trace reader. Clock period and reset duration are programmable from top level via parameters.
06/02/2012 01:48 PM
Here’s an example pseudo-code:
always @(posedge clk) begin
<send stall signal to instruction decoder>
<Do your whole AND operation>
06/06/2012 10:45 PM
This units sends the stall upon receiving the instruction from the instruction decoder unit. It keeps the stall
asserted for 5 clock cycles and then deasserts the stall signal.