User documentation

Brief description of the modules that Jeba is working on

06/02/2012 01:42 PM

Generates a fixed frequency clock and reset signal. You can use the clock via top level testbench just like any other modules. Using reset (active low) is optional. I am using that in my trace reader. Clock period and reset duration are programmable from top level via parameters.

Example pseudo code for Instruction execution unit (by Jeba)

06/02/2012 01:48 PM

Here’s an example pseudo-code:

always @(posedge clk) begin

case (1'b1)
pdp_mem_opcode.AND: begin
<send stall signal to instruction decoder>
<Do your whole AND operation>
<clear stall>

Dummy Instr_Execution unit to test Instr_decoder unit

06/06/2012 10:45 PM

This units sends the stall upon receiving the instruction from the instruction decoder unit. It keeps the stall
asserted for 5 clock cycles and then deasserts the stall signal.